The present invention relates generally to clock generator circuits and more particularly relates to an apparatus for and method of generating an accurate clock from an available clock source having an arbitrary frequency.
Many communication systems such as portable or mobile systems operate in one of two modes: an active or normal operating mode and a reduced power standby mode. The active mode is used for normal operation of the device while standby mode is used when one or more portions of the device are not needed. For example, in a cellular telephone, when a call is received and a conversation is taking place, the phone is in normal active mode. During idle period, however, when the phone is not in use most of the circuitry can be placed in standby mode which typically uses far less power than active mode.
While in standby mode (or sleep mode as it is commonly referred to), the device may xe2x80x98wake upxe2x80x99 periodically to maintain synchronization with the base station or other central device either via an interrupt mechanism, an internal state machine, or other means. Thus, during standby times, the phone may temporarily not communicate with the network but it still maintains synchronization with it. In such a mode, the power consumption of the device is greatly reduced, which is especially crucial in devices that are battery powered.
The use of dual modes of operation, i.e., normal active mode and low power standby mode typically requires the use of two different clock frequency sources. A block diagram illustrating a prior art device comprising two communication systems wherein each individual communication system has its own fast clock and standby clock sources is shown in FIG. 1. Communication system #1 12 operates in either active mode or standby mode. Each mode requires a different clock frequency. A fast clock source #1 10 is used to generate a fast clock having a frequency fFAST1 while a second slow clock source #1 14 is used to generate a standby clock (i.e., slow clock) having a frequency fSTDBY1. Similarly, communication system #2 20 operates in either active mode or standby mode. Each mode requires a different clock frequency. A fast clock source #2 16 is used to generate a fast clock having a frequency fFAST2 while a second slow clock source #2 18 is used to generate a standby clock (i.e., slow clock) having a frequency fSTDBY2.
In both systems, a faster frequency source is used when the device is active (with increased current consumption) and a slower frequency source is used when the device is in standby. The slow frequency source, however, must be chosen such that the proper timing corresponding to network time instances (i.e., events or occurrences) can be derived from it.
A problem arises when a communications module is to be added onto an existing one, as shown in the example whereby communication system #2 is added onto already existing communication systems #1. A slower frequency source (i.e., clock source #1 14) already exists which is appropriate for deriving the clock timing needed for standby mode. When communications system #2 is added, a second slow clock source is required since the already existing slow clock source #1 is likely not appropriate and would lead to incorrect turn-on times (i.e., either too early or too late) when returning from sleep or standby mode to active mode in communication system #2. Turn on times that are too early result in increased power consumption and consequently shorter battery life. Turn on times that are too late may cause the system to lose synchronization with the network.
The present invention is an apparatus for and method of generating a clock signal having a desired frequency that is derived from a clock source having any arbitrary frequency. When utilized to supply the slow clock for the standby mode of operation of a device, the mechanism described herein enables the use of an arbitrarily low frequency source while providing accurate timing. This results in reduced power consumption that would otherwise be wasted during unnecessary time spent in the active mode of operation. The mechanism of the present invention generates an average rate, very close to the optimal rate desired, by xe2x80x98swallowingxe2x80x99 or absorbing clock cycles of the available frequency source. In addition, precise timing is achieved by adding correcting time intervals, which are based on counting pulses from the higher rate clock source.
A clock frequency generator functions to generate the standby clock from the available frequency source. The clock frequency generator comprises a standby mode state machine and a jitter calculation processor. Timing calculations are performed by the jitter calculation processor and the standby mode state machine functions to generate the desired standby mode clock frequency. The state machine utilizes counters to track the number of cycles of the available clock and the number of generated cycles of the standby clock. The processor is aware of the state of the counters in the state machine that is typically implemented in hardware.
The jitter calculation processor determines the accumulated jitter error (i.e., the interval of time to be compensated) in accordance with (1) the accumulated timing error due to the difference in frequencies between the available and desired clock frequencies and (2) the number of clock cycles absorbed or swallowed. This interval is measured using the fast clock rate which is to be activated at the proper time when switching back to active mode from standby mode. Only when the last portion of the interval is measured, can the device be permitted to re-enter the active mode by powering the active mode circuitry in the device. This minimizes the average power consumption of the device. It is important to note that the mechanism of the present invention can utilize any available frequency source in generating the standby frequency. This permits better system integration (i.e., reduced size, lower cost, etc.) since additional frequency sources are not required.
The application of the clock generator apparatus and method of the present invention to communication systems is intended to provide the benefit of reduced costs. In particular, the invention is intended to reduce costs in devices where a second communication system (e.g., a communication systems conforming to the Bluethooth standard) is added to an already existing one (e.g., a GSM cellular telephone handset) and it is desired to any additional required power consumption to a minimum.
There is thus provided in accordance with the present invention a method of generating a first clock signal having a desired first frequency from an available second clock signal having a second frequency wherein the second frequency is higher than the first frequency, the method comprising the steps of generating the first clock signal by sequencing through a predetermined number of states whereby during each state a first plurality of cycles of the second clock are absorbed and a second plurality of cycles of the second clock are output as cycles of the first clock, correcting timing differences between the desired first frequency and the available second frequency at the end of each the sequence by adding a correcting time interval to the first clock such that the average frequency of the first clock is substantially equal to the desired first frequency and calculating a compensation interval to compensate for the accumulated timing jitter of the first clock signal during a specified time interval.
There is also provided in accordance with the present invention a method of generating a first clock signal having a desired first frequency from a second clock signal having a second frequency, the method comprising the steps of counting a first predetermined number of cycles of the second clock signal on a periodic basis, outputting a second predetermined number of cycles of the second clock signal on a periodic basis and correcting accumulated timing differences between the desired first frequency and the second frequency by counting a third predetermined number of cycles of the second clock signal and outputting a fourth predetermined number of cycles of the second clock signal such that the average frequency of the first clock is substantially equal to the desired first frequency.
There is further provided in accordance with the present invention, in a device having an active and a standby mode of operation, a method of accurately timing the period of time the device is in the standby mode, wherein the device utilizes a standby clock having a desired first frequency generated from an available clock having a second frequency while in standby mode and utilizes a fast clock having a third frequency while in the active mode, the method comprising the steps of dividing the output of the available clock into continuously repeating sequence of states, for all states but the last in the sequence: counting a first predetermined number of cycles of the available clock signal, outputting as the standby clock a second predetermined number of cycles of the available clock signal, for the last state in the sequence: correcting timing differences accumulated during the current sequence between the desired first frequency and the second frequency by counting a third predetermined number of cycles of the available clock signal and outputting as the standby clock a fourth predetermined number of cycles of the available clock signal such that the average frequency of the standby clock is substantially equal to the desired first frequency and calculating a compensation interval to compensate for the timing error of the standby clock signal accumulated while the device is in standby mode, the compensation interval derived from a jitter value determined in accordance with the total number of cycles of the available clock counted and the total number of cycles of the available clock generated during the current sequence up to the point in time the device switches to active mode.
There is also provided in accordance with the present invention an apparatus for generating a standby clock frequency in a device having an active and a standby mode of operation, wherein the device utilizes the standby clock having a desired first frequency while in standby mode and utilizes a fast clock having a second frequency while in the active mode, the apparatus comprising means for generating the standby clock from an available clock source comprising means for absorbing a first plurality of cycles of the available clock, means for outputting as the standby clock a second plurality of cycles of the available clock, adjustment means for periodically adjusting for the accumulated timing error caused by the differences in frequencies of the standby clock and the available clock such that the average frequency of the standby clock is substantially equal to the desired first frequency and means for calculating a compensation interval to compensate for the timing error of the standby clock signal accumulated during the time the device was in standby mode, the compensation interval derived from a jitter value determined in accordance with the total number of cycles of the available clock counted and the total number of cycles of the available clock generated during the current sequence up to the point in time the device switches to active mode.
There is further provided in accordance with the present invention an apparatus for generating a standby clock frequency in a device having an active and a standby mode of operation, wherein the device utilizes the standby clock having a desired first frequency while in standby mode and utilizes a fast clock having a second frequency while in the active mode, the apparatus comprising a clock frequency generator adapted to generate the standby clock from an available clock source, the clock frequency generator comprising a standby mode state machine operative to: absorb a first plurality of cycles of the available clock, output as the standby clock a second plurality of cycles of the available clock, periodically adjust for the accumulated timing error caused by the differences in frequencies of the standby clock and the available clock such that the average frequency of the standby clock is substantially equal to the desired first frequency and a jitter calculator adapted to calculate a compensation interval to compensate for the timing error of the standby clock signal accumulated during the time the device was in standby mode, the compensation interval derived from a jitter value determined in accordance with the total number of cycles of the available clock counted and the total number of cycles of the available clock generated during the current sequence up to the point in time the device switches to active mode.